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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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5–8  
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
Clock Networks  
clkena Signals  
The Cyclone III device family supports clkenasignals at the GCLK network level.  
This allows you to gate-off the clock even when a PLL is used. Upon re-enabling the  
output clock, the PLL does not need a resynchronization or re-lock period because the  
circuit gates off the clock at the clock network level. In addition, the PLL can remain  
locked independent of the clkenasignals because the loop-related counters are not  
affected.  
Figure 5–4 shows how to implement the clkenasignal.  
Figure 5–4. clkena Implementation  
clkena  
clkin  
clkena_out  
D
Q
clk_out  
1
1
The clkenacircuitry controlling the output C0 of the PLL to an output pin is  
implemented with two registers instead of a single register, as shown in Figure 5–4.  
Figure 5–5 shows the waveform example for a clock output enable. The clkenasignal  
is sampled on the falling edge of the clock (clkin).  
This feature is useful for applications that require low power or sleep mode.  
Figure 5–5. clkena Implementation: Output Enable  
clkin  
clkena  
clk_out  
The clkenasignal can also disable clock outputs if the system is not tolerant to  
frequency overshoot during PLL resynchronization.  
Cyclone III Device Handbook  
Volume 1  
July 2012 Altera Corporation  
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