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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
5–5  
Clock Networks  
Figure 5–1 shows the clock control block.  
Figure 5–1. Clock Control Block  
Clock Control Block  
Internal Logic  
Enable/  
Disable  
Global  
Clock  
DPCLK or CDPCLK  
Static Clock Select (3)  
Static Clock  
Select (3)  
C0  
C1  
CLK[n + 3]  
inclk1  
inclk0  
f
CLK[n + 2]  
CLK[n + 1]  
CLK[n]  
IN  
C2  
PLL  
C3  
C4  
CLKSWITCH (1)  
CLKSELECT[1..0] (2)  
Internal Logic (4)  
Notes to Figure 5–1:  
(1) The clkswitchsignal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature. The  
output of the multiplexer is the input clock (fIN) for the PLL.  
(2) The clkselect[1..0]signals are fed by internal logic and is used to dynamically select the clock source for the GCLK when the device is in user  
mode.  
(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not feasible.  
(4) You can use internal logic to enable or disable the GCLK in user mode.  
Each PLL generates five clock outputs through the c[4..0]counters. Two of these  
clocks can drive the GCLK through a clock control block, as shown in Figure 5–1.  
f
For more information about how to use the clock control block in the Quartus® II  
software, refer to the Clock Control Block (ALTCLKCTRL) Megafunction User Guide.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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