Stratix II Architecture
Figure 2–55. Output TIming Diagram in DDR Mode
CLK
A1
B1
A2
B2
A3
B3
A4
B4
From Internal
Registers
B1 A1 B2 A2 B3 A3 B4 A4
DDR output
The Stratix II IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations. The negative-edge-clocked
OE register holds the OE signal inactive until the falling edge of the clock.
This is done to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Stratix II devices also have
dedicated phase-shift circuitry for interfacing with external memory
interfaces. Stratix II devices support DDR and DDR2 SDRAM, QDR II
SRAM, RLDRAM II, and SDR SDRAM memory interfaces. In every
Stratix II device, the I/O banks at the top (banks 3 and 4) and bottom
(banks 7 and 8) of the device support DQ and DQS signals with DQ bus
modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–14 shows the number
of DQ and DQS buses that are supported per device.
Table 2–14. DQS & DQ Bus Mode Support (Part 1 of 2)
Note (1)
Number of
×4 Groups
Number of
Number of
Number of
Device
Package
×8/×9 Groups ×16/×18 Groups ×32/×36 Groups
EP2S15 484-pin FineLine BGA
672-pin FineLine BGA
8
18
8
4
8
0
4
0
4
0
4
8
0
0
0
0
0
0
4
EP2S30 484-pin FineLine BGA
672-pin FineLine BGA
4
18
8
8
EP2S60 484-pin FineLine BGA
672-pin FineLine BGA
4
18
36
8
1,020-pin FineLine BGA
18
Altera Corporation
May 2007
2–81
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
