Stratix II Architecture
Figure 2–53. Input Timing Diagram in DDR Mode
Data at
input pin
B0
A0 B1 A1 B2 A2 B3 A3 B4
CLK
A0
B0
A1
B1
A2
B2
A3
B3
Input To
Logic Array
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from ALMs on rising clock edges.
These output registers are multiplexed by the clock to drive the output
pin at a ×2 rate. One output register clocks the first bit out on the clock
high time, while the other output register clocks the second bit out on the
clock low time. Figure 2–54 shows the IOE configured for DDR output.
Figure 2–55 shows the DDR output timing diagram.
Altera Corporation
May 2007
2–79
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
