欢迎访问ic37.com |
会员登录 免费注册
发布采购

CLK6 参数 Datasheet PDF下载

CLK6图片预览
型号: CLK6
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号CLK6的Datasheet PDF文件第97页浏览型号CLK6的Datasheet PDF文件第98页浏览型号CLK6的Datasheet PDF文件第99页浏览型号CLK6的Datasheet PDF文件第100页浏览型号CLK6的Datasheet PDF文件第102页浏览型号CLK6的Datasheet PDF文件第103页浏览型号CLK6的Datasheet PDF文件第104页浏览型号CLK6的Datasheet PDF文件第105页  
Stratix II Architecture  
Figure 2–56. DQS Phase-Shift Circuitry Notes (1), (2), (3), (4)  
From PLL 5 (3)  
CLK[15..12]p (2)  
DQSn  
Pin  
DQS  
Pin  
DQSn  
Pin  
DQS  
Pin  
DQS  
Pin  
DQSn  
Pin  
DQS  
Pin  
DQSn  
Pin  
DQS  
Phase-Shift  
Circuitry  
DQS Logic  
Blocks  
Δt  
Δt  
Δt  
Δt  
Δt  
Δt  
Δt  
Δt  
to IOE  
to IOE  
to IOE  
to IOE  
to IOE  
to IOE  
to IOE  
to IOE  
Notes to Figure 2–56:  
(1) There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II device. There are  
up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.  
(2) The Δt module represents the DQS logic block.  
(3) Clock pins CLK[15..12]pfeed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]pfeed  
the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to the phase-  
shift circuitry.  
(4) You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS  
phase-shift circuitry on the bottom of the device.  
These dedicated circuits combined with enhanced PLL clocking and  
phase-shift ability provide a complete hardware solution for interfacing  
to high-speed memory.  
f
For more information on external memory interfaces, refer to the  
External Memory Interfaces in Stratix II & Stratix II GX Devices chapter in  
volume 2 of the Stratix II Device Handbook or the Stratix II GX Device  
Handbook.  
Programmable Drive Strength  
The output buffer for each Stratix II device I/O pin has a programmable  
drive strength control for certain I/O standards. The LVTTL, LVCMOS,  
SSTL, and HSTL standards have several levels of drive strength that the  
user can control. The default setting used in the Quartus II software is the  
maximum current strength setting that is used to achieve maximum I/O  
performance. For all I/O standards, the minimum setting is the lowest  
drive strength that guarantees the IOH/IOL of the standard. Using  
minimum settings provides signal slew rate control to reduce system  
noise and signal overshoot.  
Altera Corporation  
May 2007  
2–83  
Stratix II Device Handbook, Volume 1  
 复制成功!