Stratix II and Stratix II GX I/O Banks
Stratix II devices have eight general I/O banks and four enhanced
Stratix II and
Stratix II GX I/O
Banks
phase-locked loop (PLL) external clock output banks (Figure 4–21). I/O
banks 1, 2, 5, and 6 are on the left or right sides of the device and I/O
banks 3, 4, and 7 through 12 are at the top or bottom of the device.
Figure 4–21. Stratix II I/O Banks Notes (1), (2), (3), (4), (5), (6), (7)
DQS8T
DQS7T
DQS6T
DQS5T
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
PLL11
PLL5
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
PLL7
PLL10
Bank 11
Bank 9
Bank 3
Bank 4
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
I/O banks 3, 4, 9 & 11 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
standards are supported for both
input and output operations.
standards are supported for both
input and output operations.
I/O banks 1, 2, 5 & 6 support LVTTL, LVCMOS,
2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class I,
HSTL-18 Class I, HSTL-15 Class I, LVDS, and
HyperTransport standards for input and output
operations. HSTL-18 Class II, HSTL-15-Class II,
SSTL-18 Class II standards are only supported
for input operations.
PLL1
PLL2
PLL4
PLL3
I/O banks 7, 8, 10 & 12 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
Bank 12 Bank 10
Bank 8
Bank 7
PLL8
PLL9
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
DQS8B DQS7B DQS6B DQS5B
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
PLL12
PLL6
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
Notes to Figure 4–21:
(1) Figure 4–21 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
representation only. Refer to the pin list and Quartus II software for exact locations.
(2) Depending on the size of the device, different device members have different numbers of VREF groups.
(3) Banks 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent VREF group
when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank
10, the voltage level at VREFB7 is the reference voltage level for the SSTL input.
(4) Differential HSTL and differential SSTL standards are available for bidirectional operations on DQS pin and
input-only operations on PLL clock input pins; LVDS, LVPECL, and HyperTransport standards are available for
input-only operations on PLL clock input pins. Refer to the “Differential I/O Standards” on page 4–10 for more
details.
(5) Quartus II software does not support differential SSTL and differential HSTL standards at left/right I/O banks.
Refer to the “Differential I/O Standards” on page 4–10 if you need to implement these standards at these I/O banks.
(6) Banks 11 and 12 are available only in EP2S60, EP2S90, EP2S130, and EP2S180 devices.
(7) PLLs 7, 8, 9 10, 11, and 12 are available only in EP2S60, EP2S90, EP2S130, and EP2S180 devices.
4–20
Altera Corporation
January 2008
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
