External Memory Interfaces in Stratix II and Stratix II GX Devices
Stratix II and Stratix II GX DQS pins connect to the DQS pins in DDR and
DDR2 SDRAM interfaces or to the QK pins in RLDRAM II interfaces. The
DQSn pins are not used in these interfaces. Connect the Stratix II or
Stratix II GX DQS and DQSn pins to the QDRII SRAM CQ and CQ# pins,
respectively.
In every Stratix II or Stratix II GX device, the I/O banks at the top (I/O
banks 3 and 4) and bottom (I/O banks 7 and 8) of the device support DDR
memory up to 300 MHz/600 Mbps (with RLDRAM II). These I/O banks
support DQS signals and its complement DQSn signals with DQ bus
modes of ×4, ×8/×9, ×16/×18, or ×32/×36.
In ×4 mode, each DQS/DQSn pin drives up to four DQ pins within that
group. In ×8/×9 mode, each DQS/DQSn pin drives up to nine DQ pins
within that group to support one parity bit and the eight data bits. If the
parity bit or any data bit is not used, the extra DQ pins can be used as
regular user I/O pins. Similarly, with ×16/×18 and ×32/×36 modes, each
DQS/DQSn pin drives up to 18 and 36 DQ pins respectively. There are
two parity bits in the ×16/×18 mode and four parity bits in the ×32/×36
mode. Tables 3–3 through 3–6 show the number of DQS/DQ groups and
non-DQS /DQ supported in each Stratix II or Stratix II GX
density/package combination, respectively, for DLL-based
implementations.
Table 3–3. Stratix II DQS and DQ Bus Mode Support (Part 1 of 2)
Note (1)
Number of
Number of
×4 Groups
Number of
Number of
Device
Package
×8/×9 Groups ×16/×18 Groups ×32/×36 Groups
EP2S15 484-pin FineLine BGA
672-pin FineLine BGA
8
4
8
0
4
0
4
0
4
8
0
4
8
8
4
8
8
0
0
0
0
0
0
4
0
0
4
4
0
4
4
18
8
EP2S30 484-pin FineLine BGA
672-pin FineLine BGA
4
18
8
8
EP2S60 484-pin FineLine BGA
672-pin FineLine BGA
4
18
36
8
8
1,020-pin FineLine BGA
18
4
EP2S90 484-pin Hybrid FineLine BGA
780-pin FineLine BGA
18
36
36
18
36
36
8
1,020-pin FineLine BGA
18
18
8
1,508-pin FineLine BGA
EP2S130 780-pin FineLine BGA
1,020-pin FineLine BGA
18
18
1,508-pin FineLine BGA
Altera Corporation
January 2008
3–15
Stratix II Device Handbook, Volume 2