External Memory Standards
Figure 3–5. Data and Clock Relationship During a QDRII SRAM Read
Note (1)
C/K
C#/K#
t
(2)
t
(2)
CO
CO
Q
QA
QA + 1
(2)
QA + 2
QA + 3
(3)
t
(3)
CLZ
t
t
CHZ
DOH
CQ
t
(4)
CQD
CQ#
t
(5)
t
(5)
t
(4)
CQD
CCQO
CQOH
Notes to Figure 3–5:
(1) This relationship is at the memory device. The timing parameter nomenclature is based on the Cypress QDRII
SRAM data sheet for CY7C1313V18.
(2) tCO is the data clock-to-out time and tDOH is the data output hold time between burst.
(3) tCLZ and tCHZ are bus turn-on and turn-off times respectively.
(4) tCQD is the skew between the rising edge of CQ or CQ# and the data edges.
(5) tCCQO and tCQOH are skew measurements between the C or C# clocks (or the K or K# clocks in single-clock mode)
and the CQ or CQ# clocks.
When reading from the QDRII SRAM, data is sent edge-aligned with the
rising edge of the echo clocks CQ and CQ#. Both CQ and CQ# are shifted
inside the FPGA using DQS and DQSn logic blocks to capture the data in
the DDR IOE registers in DLL-based implementations. In PLL-based
implementations, CQ feeds a PLL, which generates the clock to capture
the data in the DDR IOE registers.
When writing to QDRII SRAM devices, data is generated by the write
clock while the K clock is 90° shifted from the write clock, creating a
center-aligned arrangement.
Read and write operations occur during the same clock cycle on
independent read and write data paths along with the cycle-shared
address bus. Performing concurrent reads and writes does not change the
functionality of either transaction. If a read request occurs simultaneously
with a write request at the same address, the new data on D is forwarded
to Q. Therefore, latency is not required to access valid data.
f
For more information on QDRII SRAM, go to www.qdrsram.com or see
AN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix, &
Stratix GX Devices.
3–12
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
ALTERA [ ALTERA CORPORATION ]
