External Memory Interfaces in Stratix II and Stratix II GX Devices
This section describes Stratix II and Stratix II GX features that enable
high-speed memory interfacing. It first describes Stratix II and
Stratix II GX memory pins and then the DQS phase-shift circuitry and the
DDR I/O registers. Table 3–2 shows the I/O standard associated with the
external memory interfaces.
Stratix II and
Stratix II GX
DDR Memory
Support
Overview
Table 3–2. External Memory Support in Stratix II and Stratix II GX Devices
Memory Standard
I/O Standard
DDR SDRAM
SSTL-2 Class II
DDR2 SDRAM
RLDRAM II (2)
QDRII SRAM (2)
SSTL-18 Class II(1)
1.8-V HSTL Class I or II (1)
1.8-V HSTL Class I or II (1)
Notes to Table 3–2:
(1) Stratix II and Stratix II GX devices support 1.8-V HSTL/SSTL-18 Class I and II
I/O standards in I/O banks 3, 4, 7, and 8. In I/O banks 1, 2, 5, and 6, Class I is
supported for both input and output operations, while Class II is only supported
for input operations for these I/O standards.
(2) For maximum performance, Altera recommends using the 1.8-V HSTL I/O
standard. RLDRAM II and QDRII SRAM devices also support the 1.5-V HSTL
I/O standard.
Stratix II and Stratix II GX devices support the data strobe or read clock
signal (DQS) used in DDR SDRAM, DDR2 SDRAM, RLDRAM II, and
QDRII SRAM devices with dedicated circuitry. Stratix II and Stratix II GX
devices also support the DQSn signal (the DQS complement signal) for
external memory types that require them, for example QDRII SRAM.
DQS and DQSn signals are usually associated with a group of data (DQ)
pins. However, these are not differential buffers and cannot be used in
DDR2 SDRAM or RLDRAM II interfaces.
1
You can also interface with these external memory devices
without the use of dedicated circuitry at a lower performance.
f
For more information, see the appropriate Stratix II or Stratix II GX
memory interfaces application note available at www.altera.com.
Stratix II and Stratix II GX devices contain dedicated circuitry to shift the
incoming DQS signals by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°,
120°, or 144°, depending on the delay-locked loop (DLL) mode. There are
four DLL modes. The DQS phase-shift circuitry uses a frequency
reference to dynamically generate control signals for the delay chains in
each of the DQS and DQSn pins, allowing it to compensate for process,
Altera Corporation
January 2008
3–13
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
