External Memory Interfaces in Stratix II and Stratix II GX Devices
Table 3–5. Stratix II GX DQS and DQ Bus Mode Support
Note (1)
Number of
×4 Groups
Number of
Number of
Number of
Device
Package
×8/×9 Groups ×16/×18 Groups ×32/×36 Groups
EP2SGX30C
EP2SGX30D
780-pin FineLine BGA
18
8
8
4
4
0
0
EP2SGX60C
EP2SGX60D
780-pin FineLine BGA
18
EP2SGX60E
EP2SGX90E
EP2SGX90F
1,152-pin FineLine BGA
1,152-pin FineLine BGA
1,508-pin FineLine BGA
36
36
36
36
18
18
18
18
8
8
8
8
4
4
4
4
EP2SGX130G 1,508-pin FineLine BGA
Note to Table 3–5:
(1) Check the pin table for each DQS/DQ group in the different modes.
Table 3–6. Stratix II GX Non-DQS and DQ Bus Mode Support Note (1)
Number of
×4 Groups
Number of
Number of
Number of
Device
Package
×8/×9 Groups ×16/×18 Groups ×32/×36 Groups
EP2SGX30
EP2SGX60
780-pin FineLine BGA
780-pin FineLine BGA
1,152-pin FineLine BGA
1,152-pin FineLine BGA
1,508-pin FineLine BGA
1,508-pin FineLine BGA
18
18
25
25
25
25
8
4
4
6
6
6
6
2
2
3
3
3
3
8
13
13
12
12
EP2SGX90
EP2SGX130
Note to Table 3–6:
(1) Check the pin table for each DQS/DQ group in the different modes.
1
To support the RLDRAM II QVLD pin, some of the unused ×4
DQS pins, whose DQ pins were combined to make the bigger
×8/×9, ×16/×18, or ×32/×36 groups, are listed as DQVLD pins
in the Stratix II or Stratix II GX pin table. DQVLD pins are for
input-only operations. The signal coming into this pin can be
captured by the shifted DQS signal like any of the DQ pins.
Altera Corporation
January 2008
3–17
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
