External Memory Interfaces in Stratix II and Stratix II GX Devices
Table 3–1 summarizes the maximum clock rate Stratix II and Stratix II GX
devices can support with external memory devices.
Table 3–1. Stratix II and Stratix II GX Maximum Clock Rate Support for External Memory Interfaces
Notes (1), (2)
–3 Speed Grade (MHz)
–4 Speed Grade (MHz)
–5 Speed Grade (MHz)
Memory Standards
DLL-Based PLL-Based DLL-Based PLL-Based DLL-Based PLL-Based
DDR2 SDRAM (3), (5)
DDR SDRAM (3)
RLDRAM II
333
200
300
300
300
200
150
200
200
(6)
267
200
167
133
175
167
(6)
233
200
200
250
250
167
100
175
167
(6)
250 (4)
250
QDRII SRAM
QDRII+ SRAM
250
Notes to Table 3–1:
(1) Memory interface timing specifications are dependent on the memory, board, physical interface, and core logic.
Refer to each memory interface application note for more details on how each specification was generated.
(2) The respective Altera MegaCore function and the EP2S60F1020C3 timing information featured in the Quartus® II
software version 6.0 was used to define these clock rates.
(3) This applies for interfaces with both modules and components.
(4) You must underclock a 300-MHz RLDRAM II device to achieve this clock rate.
(5) To achieve speeds greater than 267 MHz (533 Mbps) up to 333 MHz (667 Mbps), you must use the Altera DDR2
SDRAM Controller MegaCore function that features a new dynamic auto-calibration circuit in the data path for
resynchronization. For more information, see the Altera web site at www.altera.com. For interfaces running at
267 MHz or below, continue to use the static resynchronization data path currently supported by the released
version of the MegaCore function.
(6) The lowest frequency at which a QDRII+ SRAM device can operate is 238 MHz. Therefore, the PLL-based
implementation does not support the QDRII+ SRAM interface.
This chapter describes the hardware features in Stratix II and Stratix II GX
devices that facilitate the high-speed memory interfacing for each DDR
memory standard. This chapter focuses primarily on the DLL-based
implementation. The PLL-based implementation is described in
application notes. It then lists the Stratix II and Stratix II GX feature
enhancements from Stratix devices and briefly explains how each
memory standard uses the Stratix II and Stratix II GX features.
f
You can use this document with the following documents:
■
■
AN 325: Interfacing RLDRAM II with Stratix II & Stratix GX Devices
AN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix,
& Stratix GX Devices
■
■
AN 327: Interfacing DDR SDRAM with Stratix II Devices
AN 328: Interfacing DDR2 SDRAM with Stratix II Devices
Altera Corporation
January 2008
3–3
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
