TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–22. Stratix II and Stratix II GX Mixed-Port Read-During-Write:
OLD_DATA
inclock
address_a and
Address Q
address_b
data_a
A
B
wren_a
wren_b
q_b
Old
A
B
Figure 2–23. Stratix II and Stratix II GX Mixed-Port Read-During-Write:
DONT_CARE
inclock
address_a and
Address Q
address_b
data_a
A
B
wren_a
wren_b
Unknown
B
q_b
Mixed-port read-during-write is not supported when two different clocks
are used in a dual-port RAM. The output value is unknown during a
mixed-port read-during-write operation.
The TriMatrix memory structure of Stratix II and Stratix II GX devices
provides an enhanced RAM architecture with high memory bandwidth.
It addresses the needs of different memory applications in FPGA designs
with features such as different memory block sizes and modes, byte
enables, parity bit storage, address clock enables, mixed clock mode, shift
register mode, mixed-port width support, and true dual-port mode.
Conclusion
Altera Corporation
January 2008
2–35
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
