External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–3. Example of a 90° Shift on the DQS Signal
Notes (1), (2)
DQS pin to
egister delay
r
DQS at
FPGA pin
Preamble
Postamble
DQ at
FPGA pin
(3)
DQS at
IOE registers
90˚ degree
DQ at
IOE registers
DQ pin to
egister delay
r
Notes to Figure 3–3:
(1) RLDRAM II and QDRII SRAM memory interfaces do not have preamble and postamble specifications.
(2) DDR2 SDRAM does not support a burst length of two.
(3) The phase shift required for your system should be based on your timing analysis and may not be 90°.
During write operations to a DDR or DDR2 SDRAM device, the FPGA
needs to send the data to the memory center-aligned with respect to the
data strobe. Stratix II and Stratix II GX devices use a PLL to center-align
the data by generating a 0° phase-shifted system clock for the write data
strobes and a –90° phase-shifted write clock for the write data pins for
DDR and DDR2 SDRAM. Figure 3–4 shows an example of the
relationship between the data and data strobe during a burst-of-four
write.
Altera Corporation
January 2008
3–7
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
