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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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3. External Memory  
Interfaces in Stratix II and  
Stratix II GX Devices  
SII52003-4.5  
Stratix® II and Stratix II GX devices support a broad range of external  
memory interfaces such as double data rate (DDR) SDRAM, DDR2  
SDRAM, RLDRAM II, QDRII SRAM, and single data rate (SDR) SDRAM.  
Its dedicated phase-shift circuitry allows the Stratix II or Stratix II GX  
device to interface with an external memory at twice the system clock  
speed (up to 300 MHz/600 megabits per second (Mbps) with  
RLDRAM II). In addition to external memory interfaces, you can also use  
the dedicated phase-shift circuitry for other applications that require a  
shifted input signal.  
Introduction  
Typical I/O architectures transmit a single data word on each positive  
clock edge and are limited to the associated clock speed. To achieve a  
400-Mbps transfer rate, a SDR system requires a 400-MHz clock. Many  
new applications have introduced a DDR I/O architecture as an  
alternative to SDR architectures. While SDR architectures capture data on  
one edge of a clock, the DDR architectures captures data on both the  
rising and falling edges of the clock, doubling the throughput for a given  
clock frequency and accelerating performance. For example, a 200-MHz  
clock can capture a 400-Mbps data stream, enhancing system  
performance and simplifying board design.  
Most new memory architectures use a DDR I/O interface. Although  
Stratix II and Stratix II GX devices also support the mature and well  
established SDR external memory, this chapter focuses on DDR memory  
standards. These DDR memory standards cover a broad range of  
applications for embedded processor systems, image processing, storage,  
communications, and networking.  
Stratix II devices offer external memory support in every I/O bank. The  
side I/O banks support the PLL-based interfaces running at up to  
200 MHz, while the top and bottom I/O banks support PLL- and  
DLL-based interfaces. Figure 3–1 shows Stratix II device memory  
support.  
Altera Corporation  
January 2008  
3–1  
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