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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Read-During-Write Operation at the Same Address  
Figure 2–21. Stratix II and Stratix II GX Same-Port Read-During-Write  
Functionality Note (1)  
inclock  
A
A
B
data  
wren  
q
Old  
Note to Figure 2–21:  
(1) Outputs are not registered.  
Mixed-Port Read-During-Write Mode  
This mode is used when a RAM in simple or true dual-port mode has one  
port reading and the other port writing to the same address location with  
the same clock.  
The READ_DURING_WRITE_MODE_MIXED_PORTSparameter for M512  
and M4K memory blocks determines whether to output the old data at  
the address or a “don’t care” value. Setting this parameter to OLD_DATA  
outputs the old data at that address. Setting this parameter to DONT_CARE  
outputs a “don’t care” or unknown value. Figures 2–22 and 2–23 show  
sample functional waveforms where both ports have the same address.  
These figures assume that the outputs are not registered.  
The DONT_CAREsetting allows memory implementation in any TriMatrix  
memory block, whereas the OLD_DATAsetting restricts memory  
implementation to only M512 or M4K memory blocks. Selecting  
DONT_CAREgives the compiler more flexibility when placing memory  
functions into TriMatrix memory.  
The RAM outputs are unknown for a mixed-port read-during-write  
operation of the same address location of an M-RAM block, as shown in  
Figure 2–23.  
2–34  
Stratix II Device Handbook, Volume 2  
Altera Corporation  
January 2008  
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