TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
The “Same-Port Read-During-Write Mode” on page 2–33 and “Mixed-
Port Read-During-Write Mode” on page 2–34 sections describe the
functionality of the various RAM configurations when reading from an
address during a write operation at that same address. There are two
read-during-write data flows: same-port and mixed-port. Figure 2–20
shows the difference between these flows.
Read-During-
Write Operation
at the Same
Address
Figure 2–20. Stratix II and Stratix II GX Read-During-Write Data Flow
Port A
data in
Port B
data in
Mixed-port
data flow
Same-port
data flow
Port A
Port B
data out
data out
Same-Port Read-During-Write Mode
For read-during-write operation of a single-port RAM or the same port of
a true dual-port RAM, the new data is available on the rising edge of the
same clock cycle on which it was written. This behavior is valid on all
memory block sizes. Figure 2–21 shows a sample functional waveform.
When using byte enables in true dual-port RAM mode, the outputs for
the masked bytes on the same port are unknown (refer to Figure 2–1 on
page 2–7). The non-masked bytes are read out as shown in Figure 2–21.
Altera Corporation
January 2008
2–33
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
