Clock Modes
Figure 2–18. Stratix II andStratix II GX Single-Clock Mode in Simple Dual-Port Mode
Note (1)
6 LAB Row
Clocks
Memory Block
6
256 ´ 16
data[ ]
D
ENA
Q
Q
Data In
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
rdaddress[ ]
Read Address
D
ENA
To MultiTrack
Interconnect (3)
Data Out
D
Q
ENA
byteena[ ]
Byte Enable
D
ENA
Q
Q
wraddress[ ]
Write Address
D
ENA
Read Address
Clock Enable
rd_addressstall
wr_addressstall
Write Address
Clock Enable
(2)
rden
Read Enable
Write Enable
D
Q
ENA
wren
Write
Pulse
Generator
D
ENA
Q
enable
clock
Notes to Figure 2–18:
(1) Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
(2) The read enable rdensignal is not available in the M-RAM block. An M-RAM block in simple dual-port mode is
always reading the data stored at the current read address location.
(3) Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack
interconnect.
2–30
Altera Corporation
January 2008
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
