TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–1. Stratix II and Stratix II GX Byte Enable Functional Waveform
inclock
wren
a0
10
a1
a2
a0
a1
a2
address
an
ABCD
XXXX
data
XXXX
byteena
contents at a0
contents at a1
01
XX
11
XX
FFFF
ABFF
FFFF
FFCD
FFFF
ABCD
contents at a2
q (asynch)
XXCD
ABXX
ABCD
ABFF
FFCD
ABCD
doutn
1
For more information about MRAM and byte enable for the
Stratix II device family, refer to the Stratix II FPGA Errata Sheet at
the Altera web site at www.altera.com.
Pack Mode Support
Stratix II and Stratix II GX M4K and M-RAM memory blocks support
pack mode. In M4K and M-RAM memory blocks, two single-port
memory blocks can be implemented in a single block under the following
conditions:
■
■
Each of the two independent block sizes is equal to or less than half
of the M4K or M-RAM block size.
Each of the single-port memory blocks is configured in single-clock
mode.
Thus, each of the single-port memory blocks access up to half of the M4K
or M-RAM memory resources such as clock, clock enables, and
asynchronous clear signals.
Refer to “Single-Port Mode” on page 2–10 and “Single-Clock Mode” on
page 2–28 for more information.
Altera Corporation
January 2008
2–7
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
