TriMatrix Memory Overview
Table 2–7 summarizes the byte selection for ×144 mode.
Table 2–7. Stratix II and Stratix II GX M-RAM Combined Byte Selection for
×144 Mode Note (1)
byteena
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
[8] = 1
[9] = 1
[10] = 1
[11] = 1
[12] = 1
[13] = 1
[14] = 1
[15] = 1
data ×128
[7..0]
data ×144
[8..0]
[15..8]
[17..9]
[23..16]
[31..24]
[39..32]
[47..40]
[55..48]
[63..56]
[71..64]
[79..72]
[87..80]
[95..88]
[103..96]
[111..104]
[119..112]
[127..120]
[26..18]
[35..27]
[44..36]
[53..45]
[62..54]
[71..63]
[80..72]
[89..73]
[98..90]
[107..99]
[116..108]
[125..117]
[134..126]
[143..135]
Note to Table 2–7:
(1) Any combination of byte enables is possible.
Byte Enable Functional Waveform
Figure 2–1 shows how the write enable (wren) and byte enable
(byteena) signals control the operations of the RAM.
When a byte enable bit is de-asserted during a write cycle, the
corresponding data byte output appears as a “don't care” or unknown
value. When a byte enable bit is asserted during a write cycle, the
corresponding data byte output will be the newly written data.
2–6
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
ALTERA [ ALTERA CORPORATION ]
