TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Table 2–5 summarizes the byte selection.
Table 2–5. Byte Enable for Stratix II and Stratix II GX M4K Blocks Note (1)
byteena
data ×16
data ×18
data ×32
data ×36
[3..0]
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[7..0]
[8..0]
[7..0]
[15..8]
[23..16]
[31..24]
[8..0]
[17..9]
[26..18]
[35..27]
[15..8]
[17..9]
-
-
-
-
Note to Table 2–5:
(1) Any combination of byte enables is possible.
M-RAM Blocks
M-RAM blocks support byte enables for any combination of data widths
of 16, 18, 32, 36, 64, and 72 bits. For memory block configurations with
widths of less than two bytes (×16/×18), the byte-enable feature is not
supported. In the ×128 and ×144 simple dual-port modes, the two sets of
byte enable signals (byteena_aand byteena_b) combine to form the
necessary 16 byte enables. In ×128 and ×144 modes, byte enables are only
supported when using single clock mode. However, the Quartus II
software can implement byte enables in other clocking modes for ×128 or
×144 widths but will use twice as many M-RAM resources. If clock
enables are used in ×128 or ×144 mode, you must use the same clock
enable setting for both the A and B ports. Table 2–6 summarizes the byte
selection for M-RAM blocks.
Table 2–6. Byte Enable for Stratix II and Stratix II GX M-RAM Blocks Note (1)
byteena
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
data ×16
data ×18
data ×32
data ×36
[8..0]
[17..9]
data ×64
[7..0]
[15..8]
data ×72
[8..0]
[17..9]
[7..0]
[8..0]
[7..0]
[15..8]
[17..9]
[15..8]
-
-
-
-
-
-
-
-
-
-
-
-
[23..16]
[26..18] [23..16] [26..18]
[35..27] [31..24] [35..27]
[31..24]
-
-
-
-
-
-
-
-
[39..32] [44..36]
[47..40] [53..45]
[55..48] [62..54]
[63..56] [71..63]
Note to Table 2–6:
(1) Any combination of byte enables is possible.
Altera Corporation
January 2008
2–5
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
