TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Tables 2–2 and 2–3 show the capacity and distribution of the TriMatrix
memory blocks in each Stratix II and Stratix II GX family member,
respectively.
Table 2–2. TriMatrix Memory Capacity and Distribution in Stratix II Devices
M512
M4K
M-RAM
Blocks
Device
Total RAM Bits
Columns/Blocks Columns/Blocks
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
4/104
6/202
7/329
8/488
9/699
11/930
3/78
0
1
2
4
6
9
419,328
1,369,728
2,544,192
4,520,448
6,747,840
9,383,040
4/144
5/255
6/408
7/609
8/768
Table 2–3. TriMatrix Memory Capacity and Distribution in Stratix II GX
Devices
M512
M4K
M-RAM
Device
Total RAM Bits
Columns/Blocks Columns/Blocks Blocks
EP2SGX30C
EP2SGX30D
6/202
7/329
4/144
5/255
1
2
1,369,728
EP2SGX60C
EP2SGX60D
EP2SGX60E
2,544,192
EP2SGX90E
EP2SGX90F
8/488
9/699
6/408
7/609
4
6
4,520,448
6,747,840
EP2SGX130G
Parity Bit Support
All TriMatrix memory blocks (M512, M4K, and M-RAM) support one
parity bit for each byte.
Parity bits add to the amount of memory in each random access memory
(RAM) block. For example, the M512 block has 576 bits, 64 of which are
optionally used for parity bit storage. The parity bit, along with logic
implemented in adaptive logic modules (ALMs), implements parity
checking for error detection to ensure data integrity. Parity-size data
words can also be used for other purposes such as storing user-specified
control bits.
Altera Corporation
January 2008
2–3
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
