TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–3. Stratix II and Stratix II GX Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
rden
a0
a1
a2
a3
a4
a5
a6
addressstall
latched address
(inside memory)
a5
a1
a4
an
a0
q (synch)
dout0
dout1
dout4
doutn-1
doutn
doutn
dout1
dout1
dout1
dout1
dout0
dout4
dout1
q (asynch)
dout5
Figure 2–4. Stratix II and Stratix II GX Address Clock Enable During Write Cycle Waveform
inclock
a0
00
a1
01
a2
02
a3
03
a4
04
a5
05
a6
06
wraddress
data
wren
addressstall
latched address
(inside memory)
a1
a4
03
a5
an
XX
a0
00
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
XX
01
02
XX
XX
04
XX
XX
05
Stratix II and Stratix II GX TriMatrix memory blocks include input
registers that synchronize writes, and output registers to pipeline data to
improve system performance. All TriMatrix memory blocks are fully
synchronous, meaning that all inputs are registered, but outputs can be
either registered or unregistered.
Memory Modes
Altera Corporation
January 2008
2–9
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
