欢迎访问ic37.com |
会员登录 免费注册
发布采购

CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号CLK12P的Datasheet PDF文件第357页浏览型号CLK12P的Datasheet PDF文件第358页浏览型号CLK12P的Datasheet PDF文件第359页浏览型号CLK12P的Datasheet PDF文件第360页浏览型号CLK12P的Datasheet PDF文件第362页浏览型号CLK12P的Datasheet PDF文件第363页浏览型号CLK12P的Datasheet PDF文件第364页浏览型号CLK12P的Datasheet PDF文件第365页  
2. TriMatrix Embedded  
Memory Blocks in Stratix II  
and Stratix II GX Devices  
SII52002-4.5  
Stratix® II and Stratix II GX devices feature the TriMatrix™ memory  
structure, consisting of three sizes of embedded RAM blocks that  
efficiently address the memory needs of FPGA designs.  
Introduction  
TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and  
512-Kbit M-RAM blocks, which are each configurable to support many  
features. TriMatrix memory provides up to 9 megabits of RAM at up to  
550 MHz operation, and up to 16 terabits per second of total memory  
bandwidth per device. This chapter describes TriMatrix memory blocks,  
modes, and features.  
The TriMatrix architecture provides complex memory functions for  
different applications in FPGA designs. For example, M512 blocks are  
used for first-in first-out (FIFO) functions and clock domain buffering  
where memory bandwidth is critical; M4K blocks are ideal for  
applications requiring medium-sized memory, such as asynchronous  
transfer mode (ATM) cell processing; and M-RAM blocks are suitable for  
large buffering applications, such as internet protocol (IP) packet  
buffering and system cache.  
TriMatrix  
Memory  
Overview  
The TriMatrix memory blocks support various memory configurations,  
including single-port, simple dual-port, true dual-port (also known as  
bidirectional dual-port), shift register, and read-only memory (ROM)  
modes. The TriMatrix memory architecture also includes advanced  
features and capabilities, such as parity-bit support, byte enable support,  
pack mode support, address clock enable support, mixed port width  
support, and mixed clock mode support.  
When applied to input registers, the asynchronous clear signal for the  
TriMatrix embedded memory immediately clears the input registers.  
However, the output of the memory block does not show the effects until  
the next clock edge. When applied to output registers, the asynchronous  
clear signal clears the output registers and the effects are seen  
immediately.  
Altera Corporation  
January 2008  
2–1  
 复制成功!