Clock Control Block
clkena Signals
Figure 1–55 shows how clkenais implemented.
Figure 1–55. clkena Implementation
clkena
clk
clkena_out
D
Q
clk_out
In Stratix II devices, the clkenasignals are supported at the clock
network level. This allows you to gate off the clock even when a PLL is
not being used.
The clkenasignals can also be used to control the dedicated external
clocks from enhanced PLLs. Upon re-enabling, the PLL does not need a
resynchronization or relock period unless the PLL is using external
feedback mode. Figure 1–56 shows the waveform example for a clock
output enable. clkenais synchronous to the falling edge of the counter
output.
Figure 1–56. Clkena Signals
counter
output
clkena
clkout
Note to Figure 1–56
(1) The clkenasignals can be used to enable or disable the global and regional networks or the PLL_OUTpins.
1–90
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
