PLLs in Stratix II and Stratix II GX Devices
The PLL can remain locked independent of the clkenasignals since the
loop-related counters are not affected. This feature is useful for
applications that require a low power or sleep mode. Upon re-enabling,
the PLL does not need a resynchronization or relock period. The clkena
signal can also disable clock outputs if the system is not tolerant to
frequency overshoot during resynchronization.
Stratix II and Stratix II GX device enhanced and fast PLLs provide you
with complete control of device clocks and system timing. These PLLs are
capable of offering flexible system-level clock management that was
previously only available in discrete PLL devices. The embedded PLLs
meet and exceed the features offered by these high-end discrete devices,
reducing the need for other timing devices in the system.
Conclusion
This chapter references the following documents:
Referenced
Documents
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altpll Megafunction User Guide
AN 367: Implementing PLL Reconfiguration in Stratix II Devices
Configuring Stratix II and Stratix II GX Devices chapter in volume 2 of
the Stratix II GX Device Handbook (or the Stratix II Device Handbook)
DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook (or the Stratix II Device Handbook)
Selectable I/O Standards in Stratix II and Stratix II GX Devices chapter in
volume 2 of the Stratix II GX Device Handbook (or the Stratix II Device
Handbook)
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Verification, volume 3 of the Quartus II Development Software
Handbook
Altera Corporation
July 2009
1–91
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
