PLL Specifications
PLL
Specificatiofns
See the DC & Switching Characteristics chapter in volume 1 of the
Stratix II GX Device Handbook (or the Stratix II Device Handbook) for
information about PLL timing specifications
Stratix II and Stratix II GX devices provide a hierarchical clock structure
and multiple PLLs with advanced features. The large number of clocking
resources in combination with the clock synthesis precision provided by
enhanced and fast PLLs provides a complete clock-management solution.
Clocking
Global and Hierarchical Clocking
Stratix II and Stratix II GX devices provide 16 dedicated global clock
networks and 32 regional clock networks. These clocks are organized into
a hierarchical clock structure that allows for 24 unique clock sources per
device quadrant with low skew and delay. This hierarchical clocking
scheme provides up to 48 unique clock domains within the entire
Stratix II or Stratix II GX device. Table 1–17 lists the clock resources
available on Stratix II devices.
There are 16 dedicated clock pins (CLK[15..0]) on Stratix II and
Stratix II GX devices to drive either the global or regional clock networks.
Four clock pins drive each side of the Stratix II device, as shown in
Figures 1–39 and 1–40. Enhanced and fast PLL outputs can also drive the
global and regional clock networks.
Table 1–17. Clock Resource Availability in Stratix II and Stratix II GX Devices (Part 1 of 2)
Description
Stratix II Device Availability
Stratix II GX Device Availability
Number of clock input pins
24
12
Number of global clock networks 16
16
32
Number of regional clock
networks
32
Global clock input sources
Clock input pins, PLL outputs, logic
array
Clock input pins, PLL outputs, logic
array, inter-transceiver clocks
Regional clock input sources
Clock input pins, PLL outputs, logic
array
Clock input pins, PLL outputs, logic
array, inter-transceiver clocks
Number of unique clock sources 24 (16 global clocks and 8 regional
in a quadrant clocks)
24 (16 GCLK and 8 RCLK clocks)
Number of unique clock sources 48 (16 global clocks and 32 regional 48 (16 GCLK and 32 RCLK clocks)
in the entire device
clocks)
1–62
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
