PLLs in Stratix II and Stratix II GX Devices
dedicated external clock outputs from a particular enhanced PLL are
powered by separate power pins, they are less susceptible to noise. They
also reduce the overall jitter of the output clock by providing improved
isolation from switching I/O pins.
1
I/O pins that reside in PLL banks 9 through 12 are powered by
the VCC_PLL<5, 6, 11, or 12>_OUTpins, respectively. The
EP2S60F484, EP2S60F780, EP2S90H484, EP2S90F780, and
EP2S130F780 devices do not support PLLs 11 and 12. Therefore,
any I/O pins that reside in bank 11 are powered by the VCCIO3
pin, and any I/O pins that reside in bank 12 are powered by the
VCCIO8pin.
The VCC_PLL_OUTpins can by powered by 3.3, 2.5, 1.8, or 1.5 V,
depending on the I/O standard for the clock output from a particular
enhanced PLL, as shown in Figure 1–37.
Altera Corporation
July 2009
1–59
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
