Board Layout
Figure 1–36. PLL Power Schematic for Stratix II and Stratix II GX PLLs
Ferrite
Bead
1.2-V
Supply
10 μF
GND
(1)
(1)
VCCA_PLL #
GNDA_PLL #
0.001 μF
0.1 μF
GND
GND
V
CCINT
VCCD_PLL #
GND
GND
Repeat for Each
PLL Power &
Ground Set
Stratix II Device
Note to Figure 1–36
(1) Applies to PLLs 1 through 12.
VCCD
The digital power and ground pins are labeled VCCD_PLL<PLL number>
and GND. The VCCDpin supplies the power for the digital circuitry in the
PLL. Connect these VCCDpins to the quietest digital supply on the board.
In most systems, this is the digital 1.2-V supply supplied to the device’s
VCCINT pins. Connect the VCCDpins to a power supply even if you do not
use the PLL. When connecting the VCCD pins to VCCINT, you do not need
any filtering or isolation. You can connect the GNDpins directly to the
same ground plane as the device’s digital ground. See Figure 1–36.
External Clock Output Power
Enhanced PLLs 5, 6, 11, and 12 also have isolated power pins for their
dedicated external clock outputs (VCC_PLL5_OUT, VCC_PLL6_OUT,
VCC_PLL11_OUTand VCC_PLL12_OUT, respectively). Since the
1–58
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
ALTERA [ ALTERA CORPORATION ]
