PLLs in Stratix II and Stratix II GX Devices
Figure 1–38. Stratix II and Stratix II GX PLL External Clock Output Power Ball
Connection Note (1)
V
CCIO
Supply
VCC_PLL#_OUT (1)
0.001 μF
0.001 μF
0.1 μF
GND
GND
GND
GND
VCC_PLL#_OUT (1)
0.1 μF
Stratix II or Stratix II GX Device
Note to Figure 1–38:
(1) Applies only to enhanced PLLs 5, 6, 11, and 12.
Guidelines
Use the following guidelines for optimal jitter performance on the
external clock outputs from enhanced PLLs 5, 6, 11, and 12. If all outputs
are running at the same frequency, these guidelines are not necessary to
improve performance.
■
■
Use phase shift to ensure edges are not coincident on all the clock
outputs.
Use phase shift to skew clock edges with respect to each other for
best jitter performance.
If you cannot drive multiple clocks of different frequencies and phase
shifts or isolate banks, you should control the drive capability on the
lower-frequency clock. Reducing how much current the output buffer has
to supply can reduce the noise. Minimize capacitive load on the slower
frequency output and configure the output buffer to lower current
strength. The higher-frequency output should have an improved
performance, but this may degrade the performance of your lower-
frequency clock output.
Altera Corporation
July 2009
1–61
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
