Introduction
Tables 1–1 and 1–2 show the PLLs available for each Stratix II and
Stratix II GX device, respectively.
Table 1–1. Stratix II Device PLL Availability
Note (1)
Fast PLLs
Enhanced PLLs
Device
1
2
3
4
7
8
9
10
5
6
11
12
EP2S15
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
EP2S30
EP2S60
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
EP2S90 (2)
EP2S130 (3)
EP2S180
Notes for Table 1–1:
(1) The EP2S60 device in the 1,020-pin package contains 12 PLLs. EP2S60 devices in the 484-pin and 672-pin packages
contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
(2) EP2S90 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. EP2S90 devices in the 484-pin and 780-pin
packages contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
(3) EP2S130 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. The EP2S130 device in the 780-pin
package contains fast PLLs 1–4 and enhanced PLLs 5 and 6.
Table 1–2. Stratix II GX Device PLL Availability
Note (1)
Fast PLLs
Enhanced PLLs
Device
1
2
3 (3) 4 (3)
7
8
9 (3) 10 (3)
5
6
11
12
EP2SGX30 (2)
EP2SGX60 (2)
EP2SGX90
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
EP2SGX130
Notes for Table 1–2:
(1) The global or regional clocks in a fast PLL’s transceiver block can drive the fast PLL input. A pin or other PLL must
drive the global or regional source. The source cannot be driven by internally generated logic before driving the
fast PLL.
(2) EP2SGX30C and EP2SGX60C devices only have two fast PLLs (PLLs 1 and 2), but the connectivity from these two
PLLs to the global and regional clock networks remains the same as shown in this table.
(3) PLLs 3, 4, 9, and 10 are not available in Stratix II GX devices. however, these PLLs are listed in Table 1–2 because
the Stratix II GX PLL numbering scheme is consistent with Stratix and Stratix II devices.
1–2
Altera Corporation
July 2009
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
