Contents
Stratix II Device Handbook, Volume 2
References ............................................................................................................................................. 4–42
Referenced Documents ....................................................................................................................... 4–43
Document Revision History ............................................................................................................... 4–44
Chapter 5. High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX
Devices
Introduction ............................................................................................................................................ 5–1
I/O Banks ................................................................................................................................................ 5–1
Differential Transmitter ........................................................................................................................ 5–6
Differential Receiver .............................................................................................................................. 5–8
Receiver Data Realignment Circuit ............................................................................................... 5–9
Dynamic Phase Aligner ................................................................................................................. 5–10
Synchronizer ................................................................................................................................... 5–12
Differential I/O Termination ............................................................................................................. 5–12
Fast PLL ................................................................................................................................................ 5–13
Clocking ................................................................................................................................................ 5–14
Source Synchronous Timing Budget ........................................................................................... 5–16
Differential Data Orientation ........................................................................................................ 5–17
Differential I/O Bit Position ......................................................................................................... 5–17
Receiver Skew Margin for Non-DPA .......................................................................................... 5–19
Differential Pin Placement Guidelines ............................................................................................. 5–21
High-Speed Differential I/Os and Single-Ended I/Os ............................................................. 5–21
DPA Usage Guidelines .................................................................................................................. 5–22
Non-DPA Differential I/O Usage Guidelines ............................................................................ 5–26
Board Design Considerations ............................................................................................................ 5–27
Conclusion ............................................................................................................................................ 5–28
Referenced Documents ....................................................................................................................... 5–29
Document Revision History ............................................................................................................... 5–29
Section IV. Digital Signal Processing (DSP)
Revision History .................................................................................................................... Section IV–1
Chapter 6. DSP Blocks in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 6–1
DSP Block Overview ............................................................................................................................. 6–1
Architecture ............................................................................................................................................ 6–8
Multiplier Block ................................................................................................................................ 6–8
Adder/Output Block ..................................................................................................................... 6–16
Operational Modes .............................................................................................................................. 6–21
Simple Multiplier Mode ................................................................................................................ 6–22
Multiply Accumulate Mode ......................................................................................................... 6–25
Multiply Add Mode ....................................................................................................................... 6–26
Software Support ................................................................................................................................. 6–32
Conclusion ............................................................................................................................................ 6–32
Referenced Documents ....................................................................................................................... 6–33
vi
Altera Corporation
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