Contents
Stratix II Device Handbook, Volume 2
VCCD ................................................................................................................................................................................................................... 1–58
External Clock Output Power ...................................................................................................... 1–58
Guidelines ........................................................................................................................................ 1–61
PLL Specifications ................................................................................................................................ 1–62
Clocking ................................................................................................................................................ 1–62
Global and Hierarchical Clocking ................................................................................................ 1–62
Clock Sources Per Region .............................................................................................................. 1–64
Clock Input Connections ............................................................................................................... 1–69
Clock Source Control For Enhanced PLLs .................................................................................. 1–73
Clock Source Control for Fast PLLs ............................................................................................. 1–73
Delay Compensation for Fast PLLs ............................................................................................. 1–75
Clock Output Connections ............................................................................................................ 1–76
Clock Control Block ............................................................................................................................. 1–86
clkena Signals .................................................................................................................................. 1–90
Conclusion ............................................................................................................................................ 1–91
Referenced Documents ....................................................................................................................... 1–91
Document Revision History ............................................................................................................... 1–92
Section II. Memory
Revision History ..................................................................................................................... Section II–1
Chapter 2. TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 2–1
TriMatrix Memory Overview .............................................................................................................. 2–1
Parity Bit Support ............................................................................................................................. 2–3
Byte Enable Support ........................................................................................................................ 2–4
Pack Mode Support .......................................................................................................................... 2–7
Address Clock Enable Support ...................................................................................................... 2–8
Memory Modes ...................................................................................................................................... 2–9
Single-Port Mode ............................................................................................................................ 2–10
Simple Dual-Port Mode ................................................................................................................. 2–12
True Dual-Port Mode ..................................................................................................................... 2–15
Shift-Register Mode ....................................................................................................................... 2–18
ROM Mode ...................................................................................................................................... 2–20
FIFO Buffers Mode ......................................................................................................................... 2–20
Clock Modes ......................................................................................................................................... 2–20
Independent Clock Mode .............................................................................................................. 2–21
Input/Output Clock Mode ........................................................................................................... 2–23
Read/Write Clock Mode ............................................................................................................... 2–26
Single-Clock Mode ......................................................................................................................... 2–28
Designing With TriMatrix Memory .................................................................................................. 2–31
Selecting TriMatrix Memory Blocks ............................................................................................ 2–31
Synchronous and Pseudo-Asynchronous Modes ...................................................................... 2–32
Power-up Conditions and Memory Initialization ..................................................................... 2–32
Read-During-Write Operation at the Same Address ..................................................................... 2–33
iv
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
