Contents
Chapter Revision Dates ........................................................................... xi
About this Handbook ............................................................................. xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii
Section I. Clock Management
Revision History ....................................................................................................................... Section I–1
Chapter 1. PLLs in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 1–1
Enhanced PLLs ....................................................................................................................................... 1–5
Enhanced PLL Hardware Overview ............................................................................................. 1–5
Enhanced PLL Software Overview ................................................................................................ 1–9
Enhanced PLL Pins ........................................................................................................................ 1–12
Fast PLLs ............................................................................................................................................... 1–15
Fast PLL Hardware Overview ..................................................................................................... 1–15
Fast PLL Software Overview ........................................................................................................ 1–16
Fast PLL Pins ................................................................................................................................... 1–18
Clock Feedback Modes ....................................................................................................................... 1–20
Source-Synchronous Mode ........................................................................................................... 1–20
No Compensation Mode ............................................................................................................... 1–21
Normal Mode .................................................................................................................................. 1–22
Zero Delay Buffer Mode ................................................................................................................ 1–23
External Feedback Mode ............................................................................................................... 1–24
Hardware Features .............................................................................................................................. 1–25
Clock Multiplication and Division .............................................................................................. 1–26
Phase-Shift Implementation ......................................................................................................... 1–27
Programmable Duty Cycle ........................................................................................................... 1–29
Advanced Clear and Enable Control ........................................................................................... 1–29
Advanced Features .............................................................................................................................. 1–32
Counter Cascading ......................................................................................................................... 1–32
Clock Switchover ............................................................................................................................ 1–33
Reconfigurable Bandwidth ................................................................................................................ 1–44
PLL Reconfiguration ........................................................................................................................... 1–51
Spread-Spectrum Clocking ................................................................................................................ 1–51
Board Layout ........................................................................................................................................ 1–56
VCCA and GNDA ............................................................................................................................ 1–56
Altera Corporation
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ALTERA [ ALTERA CORPORATION ]
