Contents
Contents
Section VI. PCB Layout Guidelines
Revision History .................................................................................................................... Section VI–1
Chapter 10. Package Information for Stratix II & Stratix II GX Devices
Introduction .......................................................................................................................................... 10–1
Thermal Resistance .............................................................................................................................. 10–2
Package Outlines ................................................................................................................................. 10–5
484-Pin FBGA - Flip Chip .............................................................................................................. 10–5
672-Pin FBGA - Flip Chip .............................................................................................................. 10–6
780-Pin FBGA - Flip Chip .............................................................................................................. 10–9
1,020-Pin FBGA - Flip Chip ......................................................................................................... 10–11
1,152-Pin FBGA - Flip Chip ......................................................................................................... 10–13
1,508-Pin FBGA - Flip Chip ......................................................................................................... 10–15
Document Revision History ............................................................................................................. 10–17
Chapter 11. High-Speed Board Layout Guidelines
Introduction .......................................................................................................................................... 11–1
PCB Material Selection ........................................................................................................................ 11–1
Transmission Line Layout .................................................................................................................. 11–3
Impedance Calculation .................................................................................................................. 11–4
Propagation Delay .......................................................................................................................... 11–8
Pre-Emphasis .................................................................................................................................. 11–9
Routing Schemes for Minimizing Crosstalk & Maintaining Signal Integrity ........................... 11–11
Signal Trace Routing .................................................................................................................... 11–13
Termination Schemes ........................................................................................................................ 11–19
Simple Parallel Termination ....................................................................................................... 11–19
Thevenin Parallel Termination ................................................................................................... 11–20
Active Parallel Termination ........................................................................................................ 11–21
Series-RC Parallel Termination .................................................................................................. 11–22
Series Termination ....................................................................................................................... 11–23
Differential Pair Termination ..................................................................................................... 11–23
Simultaneous Switching Noise ........................................................................................................ 11–24
Power Filtering & Distribution ................................................................................................... 11–26
Electromagnetic Interference (EMI) ................................................................................................ 11–28
Additional FPGA-Specific Information .......................................................................................... 11–29
Configuration ................................................................................................................................ 11–29
JTAG ............................................................................................................................................... 11–30
Test Point ....................................................................................................................................... 11–30
Summary ............................................................................................................................................. 11–30
References ........................................................................................................................................... 11–31
Document Revision History ............................................................................................................. 11–31
Altera Corporation
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ALTERA [ ALTERA CORPORATION ]
