Contents
Contents
Same-Port Read-During-Write Mode .......................................................................................... 2–33
Mixed-Port Read-During-Write Mode ........................................................................................ 2–34
Conclusion ............................................................................................................................................ 2–35
Referenced Documents ....................................................................................................................... 2–36
Document Revision History ............................................................................................................... 2–36
Chapter 3. External Memory Interfaces in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 3–1
External Memory Standards ................................................................................................................ 3–4
DDR and DDR2 SDRAM ................................................................................................................. 3–4
RLDRAM II ....................................................................................................................................... 3–8
QDRII SRAM ................................................................................................................................... 3–10
Stratix II and Stratix II GX DDR Memory Support Overview ...................................................... 3–13
DDR Memory Interface Pins ......................................................................................................... 3–14
DQS Phase-Shift Circuitry ............................................................................................................ 3–21
DQS Logic Block ............................................................................................................................. 3–28
DDR Registers ................................................................................................................................. 3–31
PLL ................................................................................................................................................... 3–38
Enhancements In Stratix II and Stratix II GX Devices .................................................................... 3–38
Conclusion ............................................................................................................................................ 3–38
Referenced Documents ....................................................................................................................... 3–39
Document Revision History ............................................................................................................... 3–39
Section III. I/O Standards
Revision History .................................................................................................................... Section III–1
Chapter 4. Selectable I/O Standards in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 4–1
Stratix II and Stratix II GX I/O Features ............................................................................................ 4–1
Stratix II and Stratix II GX I/O Standards Support .......................................................................... 4–2
Single-Ended I/O Standards .......................................................................................................... 4–3
Differential I/O Standards ............................................................................................................ 4–10
Stratix II and Stratix II GX External Memory Interface .................................................................. 4–19
Stratix II and Stratix II GX I/O Banks ............................................................................................... 4–20
Programmable I/O Standards ...................................................................................................... 4–22
On-Chip Termination .......................................................................................................................... 4–27
On-Chip Series Termination without Calibration ..................................................................... 4–28
On-Chip Series Termination with Calibration ........................................................................... 4–30
On-Chip Parallel Termination with Calibration ........................................................................ 4–31
Design Considerations ........................................................................................................................ 4–33
I/O Termination ............................................................................................................................. 4–33
I/O Banks Restrictions .................................................................................................................. 4–34
I/O Placement Guidelines ............................................................................................................ 4–36
DC Guidelines ................................................................................................................................. 4–39
Conclusion ............................................................................................................................................ 4–42
Altera Corporation
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ALTERA [ ALTERA CORPORATION ]
