Timing Model
Table 5–34. Output Timing Measurement Methodology for Output Pins
Notes (1), (2), (3)
Measurement
Point
Loading and Termination
I/O Standard
RS (Ω)
RD (Ω)
RT (Ω) VCCIO (V) VTT (V) CL (pF)
VMEAS (V)
LVTTL (4)
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
2.325
2.325
3.135
0
0
0
0
0
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.5675
1.5675
1.1875
0.855
0.7125
1.485
1.485
1.1625
1.1625
0.83
LVCMOS (4)
2.5 V (4)
1.8 V (4)
1.5 V (4)
PCI (5)
PCI-X (5)
SSTL-2 Class I
25
25
25
25
50
25
50
50
25
50
25
50
25
50
25
1.123
1.123
0.790
0.790
0.790
0.790
0.648
0.648
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V Differential HSTL Class I
1.5-V Differential HSTL Class II
1.8-V Differential HSTL Class I
1.8-V Differential HSTL Class II
LVDS
0.83
0.83
0.83
0.6875
0.6875
0.570
1.1625
1.1625
0.83
50
50
25
50
25
50
50
25
50
25
50
25
50
25
1.123
1.123
0.790
0.790
0.648
0.648
0.790
0.790
0.83
0.6875
0.6875
0.83
50
25
0.83
100
100
100
1.1625
1.1625
1.5675
HyperTransport
LVPECL
Notes to Table 5–34:
(1) Input measurement point at internal node is 0.5 × VCCINT
.
(2) Output measuring point for VMEAS at buffer output is 0.5 × VCCIO
.
(3) Input stimulus edge rate is 0 to VCC in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
(4) Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple
(5) VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V
5–24
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
