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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Power Consumption  
Altera® offers two ways to calculate power for a design: the Excel-based  
PowerPlay Early Power Estimator power calculator and the Quartus® II  
PowerPlay Power Analyzer feature.  
Power  
Consumption  
The interactive Excel-based PowerPlay Early Power Estimator is typically  
used prior to designing the FPGA in order to get an estimate of device  
power. The Quartus II PowerPlay Power Analyzer provides better  
quality estimates based on the specifics of the design after place-and-  
route is complete. The Power Analyzer can apply a combination of user-  
entered, simulation-derived and estimated signal activities which,  
combined with detailed circuit models, can yield very accurate power  
estimates.  
In both cases, these calculations should only be used as an estimation of  
power, not as a specification.  
f
For more information about PowerPlay tools, refer to the PowerPlay Early  
Power Estimator User Guide and the PowerPlay Early Power Estimator and  
PowerPlay Power Analyzer chapters in volume 3 of the Quartus II  
Handbook.  
The PowerPlay Early Power Estimator is available on the Altera web site  
at www.altera.com. See Table 5–4 on page 5–3 for typical ICC standby  
specifications.  
TM  
TM  
The DirectDrive technology and MultiTrack interconnect ensure  
predictable performance, accurate simulation, and accurate timing  
analysis across all Stratix II device densities and speed grades. This  
section describes and specifies the performance, internal timing, external  
timing, and PLL, high-speed I/O, external memory interface, and JTAG  
timing specifications.  
Timing Model  
All specifications are representative of worst-case supply voltage and  
junction temperature conditions.  
1
The timing numbers listed in the tables of this section are  
extracted from the Quartus II software version 5.0 SP1.  
Preliminary & Final Timing  
Timing models can have either preliminary or final status. The Quartus II  
software issues an informational message during the design compilation  
if the timing models are preliminary. Table 5–33 shows the status of the  
Stratix II device timing models.  
5–20  
Altera Corporation  
Stratix II Device Handbook, Volume 1  
April 2011  
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