DC & Switching Characteristics
4. Record the time to VMEAS
.
5. Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 5–34 using the above equation. Figure 5–4 shows the model of the
circuit that is represented by the output timing of the Quartus II software.
Figure 5–4. Output Delay Timing Reporting Setup Modeled by Quartus II
V
TT
V
CCIO
Output
Output
R
C
p
n
T
L
R
S
Output
Output
Buffer
R
D
V
MEAS
GND
GND
Notes to Figure 5–4:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
(2) VCCPD is 3.085 V unless otherwise specified.
(3) VCCINT is 1.12 V unless otherwise specified.
Figures 5–5 and 5–6 show the measurement setup for output disable and
output enable timing.
Altera Corporation
April 2011
5–23
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
