APEX 20KC Programmable Logic Device Data Sheet
APEX 20KC devices include additional features such as enhanced I/O
standard support, CAM, additional global clocks, and enhanced
ClockLock clock circuitry. Table 7 shows the features included in
APEX 20KC devices.
Table 7. APEX 20KC Device Features (Part 1 of 2)
Feature
APEX 20KC Devices
MultiCore system integration
Hot-socketing support
Full support
Full support
Full support
SignalTap logic analysis
32-/64-bit, 33-MHz PCI
32-/64-bit, 66-MHz PCI
Full compliance
Full compliance in -7 and -8 speed grades in
selected devices
MultiVolt I/O
1.8-V, 2.5-V, or 3.3-V VCCIO
VCCIO selected bank by bank
5.0-V tolerant with use of external resistor
ClockLock support
Clock delay reduction
m/(n × v) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift circuitry
LVDS support
Up to four PLLs
ClockShift clock phase adjustment
Dedicated clock and input pins
Eight
Altera Corporation
5
ALTERA [ ALTERA CORPORATION ]
