APEX 20KC Programmable Logic Device Data Sheet
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Low-power operation design
...and More
Features
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1.8-V supply voltage (see Table 2)
Copper interconnect reduces power consumption
MultiVoltTM I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces
ESBs offering programmable power-saving mode
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Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
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Built-in low-skew clock tree
Up to eight global clock signals
ClockLockTM feature reducing clock delay and skew
ClockBoostTM feature providing clock multiplication and
division
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ClockShiftTM feature providing programmable clock phase and
delay shifting
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Powerful I/O features
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Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
Support for high-speed external memories, including DDR
synchronous dynamic RAM (SDRAM) and ZBT static RAM
(SRAM)
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16 input and 16 output LVDS channels at 840 megabits per
second (Mbps)
Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
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MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces
Programmable clamp to VCCIO
Individual tri-state output enable control for each pin
Programmable output slew-rate control to reduce switching
noise
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Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT,
SSTL-3 and SSTL-2, GTL+, and HSTL Class I
Supports hot-socketing operation
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Pull-up on I/O pins before and during configuration
Table 2. APEX 20KC Supply Voltages
Feature
Voltage
Internal supply voltage (VCCINT
)
1.8 V
MultiVolt I/O interface voltage levels (VCCIO) 1.8 V, 2.5 V, 3.3 V, 5.0 V (1)
Note to Table 2:
(1) APEX 20KC devices can be 5.0-V tolerant by using an external resistor.
2
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
