APEX 20KC Programmable Logic Device Data Sheet
■
■
Advanced interconnect structure
–
Copper interconnect for high performance
–
Four-level hierarchical FastTrack
®
interconnect structure
providing fast, predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
Advanced software support
–
Software design support and automatic place-and-route
provided by the Altera
®
Quartus
TM
II development system for
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
–
Altera MegaCore
®
functions and Altera Megafunction Partners
Program (AMPP
SM
) megafunctions optimized for APEX 20KC
architecture available
–
NativeLink
TM
integration with popular synthesis, simulation,
and timing analysis tools
–
Quartus II SignalTap
®
embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
–
Supports popular revision-control software packages including
PVCS, RCS, and SCCS
Notes (1), (2)
652-Pin BGA
Table 3. APEX 20KC QFP & BGA Package Options & I/O Count
Device
EP20K200C
EP20K400C
EP20K600C
EP20K1000C
208-Pin PQFP 240-Pin PQFP
136
168
356-Pin BGA
271
488
488
488
Altera Corporation
3
ALTERA [ ALTERA CORPORATION ]
