a8259 Programmable Interrupt Controller Data Sheet
ICW 4
ICW 4 is initialized when bit 0 of ICW 1 is high. Input data for ICW 4 is
sent via the
din[7..0]
bus, and the data is clocked by the rising edge of
clk.
ICW 4 is deselected with the next falling edge of the
nwr
signal.
When a write transaction for ICW 4 is finished—or if ICW 4 is skipped—
the initialization sequence is complete, and the
a8259
is ready to accept
interrupts.
Table 7
describes the ICW 4 register formats.
Table 7. ICW 4 Register Format
Bit
0
Mnemonic
µPM
Description
Microprocessor mode. When this bit is low, the
a8259
operates in a 3-byte interrupt sequence mode. If the bit is
high, it operates in a single-byte interrupt sequence
mode.
Automatic end of interrupt. When this bit is high, the
AEOI is enabled; otherwise, the AEOI is disabled.
Master/slave. When this bit is high in buffered mode, the
a8259
is configured as a slave, and when it is low, the
a8259
is configured as a master. When the device is not
in buffered mode, this bit is in a “don’t care” condition.
Buffered mode. When this bit is high, the
a8259
is in
buffered mode. See
“Operating Modes & Sequence of
Events” on page 76
for more information.
Special fully nested mode. When this bit is high, the
a8259
is in special fully nested mode.
These bits are unused and should be set low.
1
2
AEOI
M/S
3
BUF
4
5
6
7
SFNM
0
0
0
Operation Command Word Registers
Once the appropriate OCW registers have been issued to the
a8259,
they
will be ready for operation.
There are three OCW registers: OCW 1, OCW 2, and OCW 3. These
command registers control the operation of the
a8259,
and permit the
interrupt interface operation to be further modified—after the
a8259
has
been initialized. Unlike the initialization sequence, which requires the
outputs of an ICW to be in a special sequence, the OCWs can be issued
under program control whenever needed and in any order.
Altera Corporation
65
ALTERA [ ALTERA CORPORATION ]
