a8259 Programmable Interrupt Controller Data Sheet
Table 12 describes the OCW 3 register format.
Table 12. OCW 3 Register Format
Bit
Decode
Description
0
1
RIS
Read register command. These bits control which status
register will be accessed on the next read cycle (see
Table 13).
RR
2
P
When this bit is high and RR is high, the a8259enters
the poll mode; the next nrdcycle ends the poll mode
(see “Poll Command” on page 75).
3
4
5
6
1
These bits are used as address decode. Bit 4 must be
low and bit 3 must be high.
0
SMM
Special mask mode. These bits are used to enable, set,
and clear the special mask mode function (see
Table 14).
ESMM (1)
7
0
This bit is unused and should be tied to GND.
Note:
(1) Enable special mask mode.
Table 13 describes the read register commands for bits 0 and 1 of the
OCW 3 command register.
Table 13. Read Register Commands for Bits 0 & 1 of OCW 3
RR
RIS
Command
0
0
1
1
0
1
0
1
No action
No action
Read interrupt request register (IRR) on next read cycle
Read in-service register (ISR) on next read cycle
Table 14 describes the special mask mode commands for bits 5 and 6 of the
OCW 3 command register.
Table 14. Read Register Commands for Bits 0 & 1 of OCW 3
Bit 6 ESMM
Bit 5 SMM
Command
0
0
1
1
0
1
0
1
No action
No action
Reset special mask
Set special mask
68
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