a8259 Programmable Interrupt Controller Data Sheet
Figure 3. a8259 Initialization Sequence Flow Diagram
ICW 1
ICW 2
Is SINGLE
low?
Note (1)
No
Yes
ICW 3
Is
IC4
high?
Note (1)
No
Yes
ICW 4
Ready to
accept
interrupts
Note:
(1) For more information on SINGLE and IC4, see Table 3 on page 62.
Figures 4
and
5
show typical write and read cycles, respectively. The
ncs,
nwr,
and
nrd
signals enable data to be written to and read from the
a8259.
This data is clocked by the rising edge of
clk.
The
ncs
and
nwr
signals must be held low for an entire clock cycle in order to read or write
valid data.
Figure 4. Typical Write Cycle
X indicates “don’t care.” DV indicates “data valid.”
clk
nwr
ncs
din[7..0]
X
DV
X
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61
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