a8259 Programmable Interrupt Controller Data Sheet
Figure 5. Typical Read Cycle
X indicates “don’t care.” DV indicates “data valid.”
clk
nrd
ncs
din[7..0]
X
DV
X
Register
Descriptions
The
a8259
contains three type of registers:
s
s
s
Initialization command word (ICW) registers
Operation command word (OCW) registers
Interrupt registers
Initialization Command Word Registers
There are four ICW command registers: ICW 1, ICW 2, ICW 3, and ICW 4.
ICW 1
Input data for ICW 1 is sent via the
din[7..0]
bus (a0 must be low and
bit 4 of
din[7..0]
must be held high). ICW 1 is deselected with the rising
edge of the
nwr
signal.
Table 3
describes the ICW 1 register format.
Table 3. ICW 1 Register Format (Part 1 of 2)
Bit
0
Mnemonic
IC4
Description
When low, this bit causes ICW 4 to be reset (i.e., non-
buffered mode, no automatic EOI, and a 3-byte interrupt
sequence), and the initialization cycle to skip ICW 4.
When high, ICW 4 is accessed normally.
Single mode. When high, this bit indicates that the
a8259
is not cascaded with other
a8259
functions.
When low, this bit causes the
a8259
to operate in
cascade mode.
Address interval. When using a 3-byte interrupt
sequence, this bit selects the address interval. When
low, the address interval is set to eight; otherwise, it is
set to four.
1
SINGLE
2
ADI
62
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
