a8259 Programmable Interrupt Controller Data Sheet
Table 10 describes the interrupt levels acted upon when SL (bit 6 of
OCW 2) is asserted.
Table 10. Interrupt Levels for SL (Bit 6 of OCW 2)
Interrupt Level
Mnemonic
L1
L2
L0
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 11 describes the rotate and EOI commands controlled by bits 5
through 7 of the OCW 2 command register.
Table 11. Rotate & EOI Commands Controlled by Bits 5 Through 7 of OCW 2
R
SL
EOI
Command
0
0
1
1
0
1
0
1
0
0
0
1
1
1
1
0
0
1
Non-specific EOI command
Specific EOI command
Rotate on non-specific EOI command
Rotate on automatic EOI mode (set)
Rotate on automatic EOI mode (clear)
Rotate on specific EOI command (L0,
L1, and L2 are used)
1
0
1
1
0
0
Specific priority command (L0, L1, and
L2 are used)
No operation
OCW 3
OCW 3 is selected by setting the a0pin, resetting bit 4 low, and bit 3 high.
Input data for OCW 3 is sent via the din[7..0]bus, and the data is
clocked by the rising edge of clk.
Altera Corporation
67
ALTERA [ ALTERA CORPORATION ]
