a8259 Programmable Interrupt Controller Data Sheet
Functional
Description
Figure 2
shows the
a8259
block diagram.
Figure 2. a8259 Block Diagram
ir[7..0]
Register
Priority
Resolution
In-Service
Register
ninta
nsp
casin[2..0]
clk
nmrst
Interrupt
Control
Logic
int
nen
cas_en
cas_out[2..0]
Interrupt Vector
nrd
nwr
a0
ncs
din[7..0]
Read/Write
Control Logic
& Initialization/
Command
Registers
dout[7..0]
The
int
and
ninta
signals provide the handshaking mechanism for the
a8259
to signal the microprocessor. The
a8259
requests service via the
int
signal and receives an acknowledgment of acceptance from the
microprocessor via the
ninta
signal. The
int
signal is applied directly to
the microprocessor’s interrupt input. Whenever the
a8259
receives a
valid interrupt request on an
ir
pin (ir1 through
ir7),
the
int
signal
goes high.
The
ninta
input is connected to the microprocessor’s interrupt
acknowledgment signal. The microprocessor pulses the
ninta
signal
twice during the interrupt acknowledgment cycle, which tells the
a8259
that the interrupt request has been acknowledged. Then, the
a8259
sends
the highest priority active interrupt type number onto the
din[7..0]
bus for the microprocessor to acknowledge.
The
ir
inputs are used by external devices to request service, and they can
be configured for level-sensitive or edge-sensitive operation.
Altera Corporation
59
ALTERA [ ALTERA CORPORATION ]
