2–6
Chapter 2: Board Components
Configuration, Status, and Setup Elements
Figure 2–3 illustrates an exmaple of the JTAG chain connection.
Figure 2–3. JTAG Chain
(Connector not mounted)
JTAG
2 x 5 Header
TDI TDO
TMS TCK
Embedded USB-Blaster
USB
PHY
MAX V CPLD
5M570ZF256C5N
TCK TMS
TDI TDO
MAX II
EPM240M100
GPIO (TCK)
GPIO (TMS)
GPIO (TDO)
GPIO (TDI)
TMS TCK
TDI TDO
TDO TDI
TMS TCK
JTAG
2 x 5 Header
(Connector not mounted)
The primary configuration mode for the MAX V CPLD is via JTAG using the MAX II
configuration controller design (embedded USB-Blaster). The board also includes a
JTAG connector which interfaces directly to the MAX V CPLD as the alternate source
for configuration.
CPLD Configuration using External USB-Blaster
The JTAG programming header (J13) provides another method for configuring the
CPLD using an external USB-Blaster device with the Quartus II Programmer running
on a PC. The external USB-Blaster connects to the board through the JTAG connector.
Figure 2–3 illustrates the JTAG chain.
Status Elements
This section describes the status elements. The development board includes two
status LEDs which connects to the MAX V CPLD.
Table 2–5 lists the LED board references, names, and functional descriptions.
Table 2–5. Board-Specific LEDs
Board Reference
LED Name
Description
D1
Power
Blue LED. Illuminates when power is active.
Green LED. Illuminates when the embedded USB-Blaster is in use. Driven by the
MAX II CPLD EPM240M100.
D3
USB
MAX V CPLD Development Board Reference Manual
January 2011 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
