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5M160ZT100I5 参数 Datasheet PDF下载

5M160ZT100I5图片预览
型号: 5M160ZT100I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices  
8–7  
IEEE Std. 1149.1 BST Operation Control  
When the TAP controller is in the TEST_LOGIC/RESETstate, the BST circuitry is  
disabled, the device is in normal operation, and the instruction register is initialized  
with IDCODEas the initial instruction. During device power up, the TAP controller  
starts in this TEST  
the TEST LOGIC/RESETstate by holding TMShigh for five TCKclock cycles. After the  
TEST LOGIC/RESETstate, the TAP controller remains in this state as long as TMS  
_LOGIC/RESETstate. In addition, the TAP controller may be forced to  
_
_
continues to be held high while TCKis clocked.  
Figure 8–6 shows the timing requirements for the IEEE Std. 1149.1 signals.  
Figure 8–6. IEEE Std. 1149.1 Timing Waveforms (Note 1)  
TMS  
TDI  
t
JCP  
t
t
JPH  
JPSU  
t
t
JCL  
JCH  
TCK  
TDO  
t
t
t
JPZX  
JPCO  
JPXZ  
t
t
JSH  
JSSU  
Signal  
to Be  
Captured  
t
t
t
JSXZ  
JSZX  
JSCO  
Signal  
to Be  
Driven  
Note to Figure 8–6:  
(1) For timing parameter values, refer to the DC and Switching Characteristics for MAX V Devices chapter.  
To start the IEEE Std. 1149.1 operation, select an instruction mode by advancing the  
TAP controller to the shift instruction register (SHIFT_IR) state and shift in the  
appropriate instruction code on the TDIpin.  
Figure 8–7 shows the entry of the instruction code into the instruction register. From  
the RESETstate, TMSis clocked with the pattern 01100to advance the TAP controller to  
SHIFT_IRstate.  
Figure 8–7. Selecting the Instruction Mode  
TCK  
TMS  
TDI  
TDO  
SHIFT_IR  
TAP_STATE  
RUN_TEST/IDLE  
SELECT_IR_SCAN  
SELECT_DR_SCAN  
EXIT1_IR  
CAPTURE_IR  
TEST_LOGIC/RESET  
December 2010 Altera Corporation  
MAX V Device Handbook  
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