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5M160ZT100I5 参数 Datasheet PDF下载

5M160ZT100I5图片预览
型号: 5M160ZT100I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices  
8–9  
IEEE Std. 1149.1 BST Operation Control  
Figure 8–8 shows the capture, shift, and update phases of SAMPLE/PRELOADmode.  
Figure 8–8. IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode  
SDO  
PIN_IN  
INJ  
0
1
D
Input  
Q
PIN_OE  
OEJ  
0
1
0
1
D
Q
D
D
Q
Q
0
1
OE  
OE  
OUTJ  
PIN_OUT  
0
1
0
1
D
Q
Pin  
Output  
Output  
Output  
Buffer  
SHIFT  
CLOCK  
UPDATE  
HIGHZ MODE  
Global Signals  
Capture  
Registers  
Update  
Registers  
SDI  
(Capture Phase)  
SDO  
PIN_IN  
INJ  
0
1
D
Input  
Q
PIN_OE  
OEJ  
0
1
0
1
D
Q
D
D
Q
Q
0
1
OE  
OE  
OUTJ  
PIN_OUT  
0
1
0
1
D
Q
Pin  
Output  
Output  
Output  
Buffer  
SHIFT  
CLOCK  
UPDATE  
HIGHZ MODE  
Global Signals  
Capture  
Registers  
Update  
Registers  
SDI  
(Shift and Update Phase)  
SAMPLE/PRELOADinstruction code shifts in through the TDIpin. The TAP controller  
advances to the CAPTURE DRstate and then to the SHIFT DRstate, where it remains if  
TMSis held low. The data shifted out of the TDOpin consists of the data that was  
_
_
present in the capture registers after the capture phase. New test data shifted into the  
TDIpin appears at the TDOpin after being clocked through the entire boundary-scan  
register.  
December 2010 Altera Corporation  
MAX V Device Handbook  
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